Items where Author is "Zheng, Li-Rong"

Weerasekera, Roshan and Grange, M. and Pamunuwa, Dinesh Bandara and Tenhunen, Hannu and Zheng, Li-Rong (2009) Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits. In: Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009 :. IEEE, San Francisco. ISBN 978-1-4244-4511-0

Weldezion, A. and Weerasekera, Roshan and Pamunuwa, Danesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2009) Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits. In: Workshop Notes, Design, Automation and Test in Europe (DATE) :. UNSPECIFIED, Nice.

Weerasekera, Roshan and Pamunuwa, Dinesh B. and Grange, M. and Tenhunen, Hannu and Zheng, Li-Rong (2009) Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits (ICs). In: Workshop Notes, Design, Automation and Test in Europe (DATE) :. UNSPECIFIED, Nice.

Weerasekera, Roshan and Pamunuwa, Dinesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2008) Minimal-power, delay-balanced smart repeaters for global interconnects in the nanometer regime. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16 (5). pp. 589-593. ISSN 1063-8210

Weerasekera, Roshan and Zheng, Li-Rong and Pamunuwa, Dinesh B. and Tenhunen, Hannu (2007) Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs. In: Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) :. IEEE, San Jose, California, pp. 212-219. ISBN 978-1-4244-1382-9

Weerasekera, Roshan and Zheng, Li-Rong and Pamunuwa, Dinesh B. and Tenhunen, Hannu (2007) Early selection of system implementation choice among SoC, SoP and 3-D integration. In: Proc. International System-On-Chip Conference (SOCC) :. IEEE, Hsin Chu, Taiwan. ISBN 978-1-4244-1592-2

Weerasekera, Roshan and Pamunuwa, Dinesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2007) Delay-balanced smart repeaters for on-chip global signaling. In: Proc. International Conference on VLSI Design :. IEEE, Bangalore, pp. 308-313. ISBN 0-7695-2762-0

Weerasekera, Roshan and Pamunuwa, Dinesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2006) Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. In: Proc. International Workshop on System-level Interconnect Prediction (SLIP) :. ACM, Munich, pp. 113-120. ISBN 1-59593-255-0

Weerasekera, Roshan and Zheng, Li-Rong and Pamunuwa, Dinesh Bandara and Tenhunen, Hannu (2005) Switching sensitive driver circuit to combat dynamic delay in on-chip buses. In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. Lecture Notes in Computer Science . Springer, Berlin, pp. 277-285. ISBN 9783540290131

Pamunuwa, Dinesh B. and Öberg, Johnny and Millberg, Mikael and Zheng, Li-Rong and Jantsch, Axel and Tenhunen, Hannu (2004) A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integration, the VLSI Journal, 38 (1). pp. 3-17. ISSN 0167-9260

Pamunuwa, Dinesh B. and Öberg, Johnny and Zheng, Li-Rong and Millberg, Mikael and Jantsch, Axel and Tenhunen, Hannu (2003) Layout, performance and power trade-offs in mesh-based network-on chip architectures. In: Proc. IFIP International Conference on VLSI Systems-on-chip :. Technische Universität Darmstadt, Insitute of Microelectronic Systems, Darmstadt, Germany, pp. 362-366. ISBN 3-901882-17-0

Liu, J. and Zheng, Li-Rong and Pamunuwa, Dinesh B. and Tenhunen, Hannu (2003) A global wire planning scheme for Network-on-Chip. In: Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. :. UNSPECIFIED, IV-892-IV-895. ISBN 0-7803-7761-3

Pamunuwa, Dinesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2002) Optimising bandwidth over deep sub-micron interconnect. In: 2002 IEEE International Symposium on Circuits and Systems :. IEEE, IV-193. ISBN 0-7803-7448-7

Zheng, Li-Rong and Pamunuwa, Dinesh B. and Tenhunen, Hannu (2000) Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design. In: Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00. :. IEEE, pp. 352-355.

Pamunuwa, Dinesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2000) Combating digital noise in high speed ULSI circuits using binary BCH encoding. In: The 2000 IEEE International Symposium on Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. :. IEEE, Geneva, pp. 13-16. ISBN 0-7803-5482-6

Pamunuwa, Dinesh B. and Zheng, Li-Rong and Tenhunen, Hannu (1999) Error-control coding to combat digital noise in interconnects for ULSI circuits. In: Proc. IEEE Norchip Conference Oslo 1999 :. IEEE, Norway, pp. 275-282.