Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.
Zheng, Li-Rong and Pamunuwa, Dinesh B. and Tenhunen, Hannu
(2000)
Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.
In:
Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00. :.
IEEE, pp. 352-355.
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Abstract
A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.
Item Type:
Contribution in Book/Report/Proceedings
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Uncontrolled Keywords:
/dk/atira/pure/researchoutput/libraryofcongress/ta
Subjects:
?? ta engineering (general). civil engineering (general) ??
Deposited On:
10 May 2010 09:14
Last Modified:
12 Oct 2024 00:35