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Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits.

Weldezion, A. and Weerasekera, Roshan and Pamunuwa, Danesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2009) Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits. In: Workshop Notes, Design, Automation and Test in Europe (DATE) :. UNSPECIFIED, Nice.

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Item Type:
Contribution in Book/Report/Proceedings
Uncontrolled Keywords:
/dk/atira/pure/researchoutput/libraryofcongress/ta
Subjects:
?? ta engineering (general). civil engineering (general) ??
Departments:
Faculty of Science and Technology > Engineering
ID Code:
31108
Deposited By:
Users 49 not found.
Deposited On:
18 Dec 2009 16:15
Refereed?:
No
Published?:
Published
Last Modified:
22 Sep 2024 23:45
URI:
https://eprints.lancs.ac.uk/id/eprint/31108