Pattern-generation and pattern-transfer for single-digit nano devices

Rangelow, Ivo W. and Ahmad, Ahmad and Ivanov, Tzvetan and Kaestner, Marcus and Krivoshapkina, Yana and Angelov, Tihomir and Lenk, Steve and Lenk, Claudia and Ishchuk, Valentyn and Hofmann, Martin and Nechepurenko, Diana and Atanasov, Ivaylo and Volland, Burkhard and Guliyev, Elshad and Durrani, Zahid A. K. and Jones, Mervyn E. and Wang, Chen and Liu, Dixi and Reum, Alexander and Holz, Mathias and Nikolov, Nikolay and Majstrzyk, Wojciech and Gotszalk, Teodor and Staaks, Daniel and Dallorto, Stefano and Olynick, Deirdre L. (2016) Pattern-generation and pattern-transfer for single-digit nano devices. Journal of Vacuum Science and Technology B, 34 (6): 06K202. ISSN 1071-1023

Abstract

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.