Exploration of Through Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits

Grange, M. and Weerasekera, R. and Pamunuwa, D. and Tenhunen, H. (2009) Exploration of Through Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits. In: Workshop Notes, Design, Automation and Test in Europe (DATE). UNSPECIFIED, Nice.

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31107
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Deposited On:
18 Dec 2009 16:09
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31 Oct 2020 08:46