Modelling noise and delay in VLSI circuits.

Pamunuwa, Dinesh B. and Elassaad, S. and Tenhunen, H. (2003) Modelling noise and delay in VLSI circuits. Electronics Letters, 39 (3). pp. 269-271. ISSN 0013-5194

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Abstract

New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay.

Item Type: Journal Article
Journal or Publication Title: Electronics Letters
Uncontrolled Keywords: /dk/atira/pure/researchoutput/libraryofcongress/ta
Subjects:
Departments: Faculty of Science and Technology > Engineering
ID Code: 31101
Deposited By: Users 49 not found.
Deposited On: 18 Dec 2009 14:58
Refereed?: Yes
Published?: Published
Last Modified: 14 Oct 2019 12:11
URI: https://eprints.lancs.ac.uk/id/eprint/31101

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