Scalable Fabrication, Characterisation and Critical Interface Simulation of ULTRARAM™ Memory Devices

Xia, Xiuxin and Hayne, Manus (2025) Scalable Fabrication, Characterisation and Critical Interface Simulation of ULTRARAM™ Memory Devices. PhD thesis, Lancaster University.

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Abstract

In this work, the design, fabrication and characterisation of scalable ULTRARAM™ aiming at 50 nm gate dimension are reported, in conjunction with simulations of the interface alloying of the triple-barrier resonant-tunnelling (TBRT), aiming at the scaling-down of the feature size of the memory devices for commercialisation. ULTRARAM™ is a non-volatile, III-V based compound-semiconductor, charge-storage memory in which the oxide barrier that separates the floating gate from the channel in flash is replaced by the TBRT structure that exploits the 2 eV band offset between InAs and AlSb. This empowers ULTRARAM™ to operate at low voltage and high speed, with high endurance, low disturbance and ultra-low switching energy. Multiple batches of memory devices were fabricated alongside the optimisation of the self-aligned design. Two key improvements shape the final processing flow. The introduction of all-dry etching enables the nanometre scalability of the memory design for the first time and the employment of laser interferometry in end-point detection allows enhanced accuracy of etching to the 10 nm-thick channel. The characterisation of the as-fabricated devices demonstrated stable performance with memory windows of∼10 µA at room temperature and a minimum pulse duration 5 ms was obtained, indicating the success of improvements made in the refining of the fabrication flow. A lingering issue with the gate-drain leakage through dielectric due to the problematic gate metal that arose during the legacy method is solved, and a synchrotron X-ray nano-probe analysis was conducted in an attempt to understand the failure mechanism of the devices. A resistive-gap hypothesis is proposed to explain the poor performance observed in as-fabricated devices. A compact device design is then proposed to address the issue and preliminary validation of the fabrication flow shows promising results where the resistive gap is substantially reduced from∼5 µm to 385 nm, a factor of ten smaller than the previous design. This is expected to further improve the memory readout performance. Simulation by nextnano software using the multi-scattering B¨uttiker (MSB) probe formulism was carried out to investigate robustness of TBRT operation against intermixing after concerns were raised as a result of transmission electron microscopy (TEM) images. All scenarios, including alloying at both barrier and quantum well layers, show only slight impact on the memory operation voltage but no undermining of the TBRT function, evidencing the resilience of the TBRT structure against the growth imperfections or fluctuations, in strong support for the ULTRARAM™ concept. The interplay of these findings indicates ULTRARAM™’s potential as a viable emerging universal memory and its way to practical application in the not too distant future.