Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

Bratt, Adrian and Harvey, R. J. A. and Dorey, A. P. and Richardson, A. M. D. (1993) Design-for-test structure to facilitate test vector application with low performance loss in non-test mode. Electronics Letters, 29 (16). pp. 1438-1440. ISSN 1350-911X

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Abstract

A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1].

Item Type:
Journal Article
Journal or Publication Title:
Electronics Letters
Additional Information:
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Uncontrolled Keywords:
/dk/atira/pure/subjectarea/asjc/2200/2208
Subjects:
?? electrical and electronic engineeringta engineering (general). civil engineering (general) ??
ID Code:
20609
Deposited By:
Deposited On:
02 Dec 2008 11:11
Refereed?:
No
Published?:
Published
Last Modified:
15 Sep 2024 00:08