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A digital partial built-in self-test structure for a high performance automatic gain control circuit

Lechner, A and Ferguson, J and Richardson, A and Hermes, B (1999) A digital partial built-in self-test structure for a high performance automatic gain control circuit. In: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS. IEEE COMPUTER SOC, LOS ALAMITOS, pp. 232-238. ISBN 0-7695-0078-1

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Abstract

It is now widely recognised that Design-for-Testability and Built-in Self-Test techniques rc ill be mandatory to meet test and quality specifications in next generation mired signal integrated systems. This paper describes a new digital on-chip post processing function capable of reducing production test time for a high performance automatic gain control circuit by 70%.

Item Type: Contribution in Book/Report/Proceedings
Uncontrolled Keywords: DESIGN-FOR-TEST ; ANALOG ; BIST ; DAC ; ADC
Subjects: UNSPECIFIED
Departments: Faculty of Science and Technology > Engineering
ID Code: 50478
Deposited By: ep_importer_pure
Deposited On: 25 Oct 2011 16:31
Refereed?: No
Published?: Published
Last Modified: 24 Jan 2014 06:00
Identification Number:
URI: http://eprints.lancs.ac.uk/id/eprint/50478

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