Zheng, Li-Rong and Pamunuwa, Dinesh B. and Tenhunen, Hannu (2000) Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design. In: Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00. IEEE, pp. 352-355.
A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.
|Item Type: ||Contribution in Book/Report/Proceedings|
|Additional Information: ||"©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."|
|Subjects: ||T Technology > TA Engineering (General). Civil engineering (General)|
|Departments: ||Faculty of Science and Technology > Engineering|
|ID Code: ||33275|
|Deposited By: ||Mr Richard Ingham|
|Deposited On: ||10 May 2010 10:14|
|Last Modified: ||28 Apr 2017 01:24|
|Identification Number: |
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