Items where Author is "Pamunuwa, Dinesh Bandara"

Weerasekera, Roshan and Grange, M. and Pamunuwa, Dinesh Bandara and Tenhunen, Hannu and Zheng, Li-Rong (2009) Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits. In: Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009 :. IEEE, San Francisco. ISBN 978-1-4244-4511-0

Weldezion, A. Y. and Grange, M. and Pamunuwa, Dinesh Bandara and Lu, Zhonghai and Jantsch, A. and Weerasekera, Roshan and Tenhunen, Hannu (2009) Scalability of Network-on-Chip communication architecture for 3-D meshes. In: Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS) :. IEEE, San Diego, pp. 114-123. ISBN 978-1-4244-4142-6

Lei, Ci and Pamunuwa, Dinesh Bandara and Bailey, Stephen and Lambert, Colin (2009) Designing reliable digital molecular electronic circuits. In: Nano-Net 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings :. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering . Springer, Berlin, pp. 111-115. ISBN 978-3-642-04849-4

Grange, M. and Weldezion, A. Y. and Pamunuwa, Dinesh Bandara and Weerasekera, R. and Zhonghai, Lu and Jantsch, A. and Shippen, D. (2009) Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh. In: Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009 :. IEEE, San Francisco. ISBN 978-1-4244-4511-0

Weerasekera, Roshan and Zheng, Li-Rong and Pamunuwa, Dinesh Bandara and Tenhunen, Hannu (2005) Switching sensitive driver circuit to combat dynamic delay in on-chip buses. In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. Lecture Notes in Computer Science . Springer, Berlin, pp. 277-285. ISBN 9783540290131