A global wire planning scheme for Network-on-Chip.

Liu, J. and Zheng, Li-Rong and Pamunuwa, Dinesh B. and Tenhunen, Hannu (2003) A global wire planning scheme for Network-on-Chip. In: Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. UNSPECIFIED, IV-892-IV-895. ISBN 0-7803-7761-3

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Abstract

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.

Item Type: Contribution in Book/Report/Proceedings
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Uncontrolled Keywords: /dk/atira/pure/researchoutput/libraryofcongress/ta
Subjects:
Departments: Faculty of Science and Technology > Engineering
ID Code: 33249
Deposited By: Mr Richard Ingham
Deposited On: 07 May 2010 14:28
Refereed?: No
Published?: Published
Last Modified: 10 Jun 2019 19:11
URI: https://eprints.lancs.ac.uk/id/eprint/33249

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