Memory technology for extended large-scale integration in future electronics applications.

Pamunuwa, Dinesh B. (2008) Memory technology for extended large-scale integration in future electronics applications. In: Proc. Design, Automation and Test in Europe (DATE) Conference. IEEE, Munich, pp. 1126-1127. ISBN 978-3-9810801-3-1

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Abstract

Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length, with associated improvements in cost, and delay and energy consumption, while also providing an opportunity to integrate disparate technologies. Such advances are very much technology driven, and early research into 3-D integration has now crystallised into commercially viable options that are being pursued by many companies. Being able to position memory in closer proximity to processing elements in a NoC architecture as afforded by a 3-D physical architecture has the potential to improve the memory bandwidth and mitigate the general nature of delay constrained performance in IC design. Understanding the nature of the opportunities and constraints provided in such a 3-D physical architecture is crucial in realising the true benefits of 3-D integration in future applications.

Item Type: Contribution in Book/Report/Proceedings
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Uncontrolled Keywords: /dk/atira/pure/researchoutput/libraryofcongress/ta
Subjects:
Departments: Faculty of Science and Technology > Engineering
ID Code: 31129
Deposited By: Users 49 not found.
Deposited On: 21 Dec 2009 12:34
Refereed?: No
Published?: Published
Last Modified: 17 Sep 2019 23:53
URI: https://eprints.lancs.ac.uk/id/eprint/31129

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