Scalability of Network-on-Chip communication architecture for 3-D meshes.

Weldezion, A. Y. and Grange, M. and Pamunuwa, Dinesh Bandara and Lu, Zhonghai and Jantsch, A. and Weerasekera, Roshan and Tenhunen, Hannu (2009) Scalability of Network-on-Chip communication architecture for 3-D meshes. In: Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS). IEEE, San Diego, pp. 114-123. ISBN 978-1-4244-4142-6

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Abstract

Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologies for 3D network-on-chips (NoC) using through-silicon-vias (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3D NoC is examined under both communication architectures and compared to 2D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.

Item Type: Contribution in Book/Report/Proceedings
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Uncontrolled Keywords: /dk/atira/pure/researchoutput/libraryofcongress/ta
Subjects:
Departments: Faculty of Science and Technology > Engineering
ID Code: 31105
Deposited By: Users 49 not found.
Deposited On: 18 Dec 2009 15:29
Refereed?: No
Published?: Published
Last Modified: 19 Sep 2019 01:57
URI: https://eprints.lancs.ac.uk/id/eprint/31105

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