Minimal-power, delay-balanced smart repeaters for global interconnects in the nanometer regime.

Weerasekera, Roshan and Pamunuwa, Dinesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2008) Minimal-power, delay-balanced smart repeaters for global interconnects in the nanometer regime. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16 (5). pp. 589-593. ISSN 1063-8210

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Abstract

A smart repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pattern on the wires and thus the effective capacitive load. This is achieved by partitioning the driver into main and assistant drivers; for a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. In a UMC 0.18-mum technology the potential energy saving is around 10% and the reduction in jitter 20%, in comparison to a traditional repeater for typical global wire lengths. It is also shown that the average energy saving for nanometer technologies is in the range of 20% to 25%. The driver architecture exploits the fact that as feature sizes decrease, the capacitive load per transistor shrinks, whereas global wire loads remain relatively unchanged. Hence, the smaller the technology, the greater the potential saving.

Item Type: Journal Article
Journal or Publication Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Uncontrolled Keywords: /dk/atira/pure/researchoutput/libraryofcongress/ta
Subjects:
Departments: Faculty of Science and Technology > Engineering
ID Code: 31099
Deposited By: Mr Michael Dunne
Deposited On: 18 Dec 2009 14:25
Refereed?: Yes
Published?: Published
Last Modified: 15 Sep 2019 00:36
URI: https://eprints.lancs.ac.uk/id/eprint/31099

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