Chávez-Bracamontes, Ramón and Gurrola-Navarro, Marco A. and Jiménez-Flores, Humberto J. and Bandala-Sánchez, Manuel (2016) VLSI architecture of a Kalman filter optimized for real-time applications. IEICE Electronics Express, 13 (6): 20160043. ISSN 1349-2543
Full text not available from this repository.Abstract
This paper presents a parametrized VLSI architecture for an nstate Kalman filter implementation intended for real-time applications that typically require a sensing rate not far from 300 samples per second. The architecture has been optimized in silicon area and power consumption. This approach has been proved with a fabricated chip using a 0.5μm CMOS technology. The fabricated integrated circuit executes a two-state Kalman filter employing 70K transistors. For a performance of 50 filter iterations/second, the chip requires a clock frequency of 200 KHz where a negligible power consumption of 1.1mWis observed. This performance can be increased up to 176,991 iterations/second at a clock frequency of 20 MHz.