Area-efficient high-speed 3D DWT processor architecture

Jiang, M. and Crookes, D. (2007) Area-efficient high-speed 3D DWT processor architecture. Electronics Letters, 43 (9). pp. 502-503. ISSN 0013-5194

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Abstract

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128times128times128 fMRI volume image in 20 ms

Item Type:
Journal Article
Journal or Publication Title:
Electronics Letters
Uncontrolled Keywords:
/dk/atira/pure/subjectarea/asjc/2200/2208
Subjects:
ID Code:
132121
Deposited By:
Deposited On:
25 Mar 2019 09:25
Refereed?:
Yes
Published?:
Published
Last Modified:
17 Jun 2020 06:54