Low-power systolic array processor architecture for FSBM video motion estimation

Jiang, M. and Crookes, D. and Davidson, S. and Turner, R. (2006) Low-power systolic array processor architecture for FSBM video motion estimation. Electronics Letters, 42 (20). pp. 1146-1148. ISSN 0013-5194

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Abstract

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

Item Type:
Journal Article
Journal or Publication Title:
Electronics Letters
Uncontrolled Keywords:
/dk/atira/pure/subjectarea/asjc/2200/2208
Subjects:
ID Code:
132120
Deposited By:
Deposited On:
25 Mar 2019 09:00
Refereed?:
Yes
Published?:
Published
Last Modified:
01 Jan 2020 11:52