Using signed digit arithmetic for low-power multiplication

Crookes, D. and Jiang, M. (2007) Using signed digit arithmetic for low-power multiplication. Electronics Letters, 43 (11). pp. 613-614. ISSN 0013-5194

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Abstract

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

Item Type:
Journal Article
Journal or Publication Title:
Electronics Letters
Uncontrolled Keywords:
/dk/atira/pure/subjectarea/asjc/2200/2208
Subjects:
ID Code:
132119
Deposited By:
Deposited On:
25 Mar 2019 09:30
Refereed?:
Yes
Published?:
Published
Last Modified:
11 Mar 2020 07:20