Richardson, Andrew and Burbidge, Martin (2008) Phase Locked Loop Test Methodology. In: Test and Diagnosis of Analogue, Mixed-signal and RF Integrated Circuits. IET Press, Stevenage, pp. 277-306. ISBN 978-0-86341-745-0
|PDF (PLL Test Chapter) - Draft Version |
Available under License Creative Commons Attribution Non-commercial No Derivatives.
Download (339Kb) | Preview
Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications.
|Item Type:||Contribution in Book/Report/Proceedings|
|Uncontrolled Keywords:||PLL Test ; Mixed Signal Test|
|Departments:||Faculty of Science and Technology > Engineering|
|Deposited On:||20 Jan 2012 14:15|
|Last Modified:||06 Feb 2016 00:05|
Actions (login required)