Prieto, J A and Rueda, A and Grout, I and Peralias, E and Huertas, J L and Richardson, A M D (1998) An approach to realistic fault prediction and layout design for testability in analog circuits. In: Design, Automation and Test in Europe, 1998 Proceedings. IEEE COMPUTER SOC, LOS ALAMITOS, pp. 905-909. ISBN 0-8186-8359-7Full text not available from this repository.
This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.
|Item Type:||Contribution in Book/Report/Proceedings|
|Departments:||Faculty of Science and Technology > Engineering|
|Deposited On:||08 Nov 2011 11:59|
|Last Modified:||24 Jan 2014 06:00|
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