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Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits.

Weerasekera, Roshan and Grange, M. and Pamunuwa, Dinesh Bandara and Tenhunen, Hannu and Zheng, Li-Rong (2009) Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits. In: Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. IEEE, San Francisco. ISBN 978-1-4244-4511-0

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Abstract

Modeling parasitic parameters of Through-Silicon-Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3-D) integrated circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for resistance, capacitance and inductance of various TSV structures. Further, a reduced-order electrical circuit model is proposed for isolated TSVs as well as bundled structures for delay and SI analysis, and extracted TSV parasitics are employed in Spectre simulations for performance evaluations. Critical issues in the performance modeling for design space exploration of 3-D ICs such as cross-talk induced switching pattern dependent delay variation and cross-talk on noise are discussed. The error in these metrics when using the proposed models as compared to a field solver is contained to a few percentage points.

Item Type: Contribution in Book/Report/Proceedings
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Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Departments: Faculty of Science and Technology > Engineering
ID Code: 31661
Deposited By: Mr Richard Ingham
Deposited On: 01 Feb 2010 10:02
Refereed?: No
Published?: Published
Last Modified: 26 Jul 2012 21:44
Identification Number:
URI: http://eprints.lancs.ac.uk/id/eprint/31661

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