Grange, M. and Weldezion, A. Y. and Pamunuwa, Dinesh Bandara and Weerasekera, R. and Zhonghai, Lu and Jantsch, A. and Shippen, D. (2009) Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh. In: Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. IEEE, San Francisco. ISBN 978-1-4244-4511-0Full text not available from this repository.
The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
|Item Type:||Contribution in Book/Report/Proceedings|
|Subjects:||T Technology > TA Engineering (General). Civil engineering (General)|
|Departments:||Faculty of Science and Technology > Engineering|
|Deposited By:||Mr Richard Ingham|
|Deposited On:||01 Feb 2010 09:38|
|Last Modified:||05 Dec 2016 01:22|
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