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On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

Weerasekera, Roshan and Grange, M. and Pamunuwa, Dinesh B. and Tenhunen, Hannu (2010) On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits. In: Design Automation and Test in Europe (DATE) Conference, 2010-01-01, Dresden, Germany.

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    Abstract

    This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.

    Item Type: Conference or Workshop Item (Paper)
    Journal or Publication Title: Design Automation and Test in Europe (DATE) Conference
    Subjects: T Technology > TA Engineering (General). Civil engineering (General)
    Departments: Faculty of Science and Technology > Engineering
    ID Code: 31657
    Deposited By: Mr Richard Ingham
    Deposited On: 01 Feb 2010 09:07
    Refereed?: Yes
    Published?: Published
    Last Modified: 17 Sep 2013 09:59
    Identification Number:
    URI: http://eprints.lancs.ac.uk/id/eprint/31657

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