Weerasekera, Roshan and Zheng, Li-Rong and Pamunuwa, Dinesh Bandara and Tenhunen, Hannu (2005) Switching sensitive driver circuit to combat dynamic delay in on-chip buses. In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Lecture Notes in Computer Science . Springer, Berlin, pp. 277-285. ISBN 9783540290131Full text not available from this repository.
In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it’s drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.
|Item Type:||Contribution in Book/Report/Proceedings|
|Subjects:||T Technology > TA Engineering (General). Civil engineering (General)|
|Departments:||Faculty of Science and Technology > Engineering|
|Deposited By:||Mr Michael Dunne|
|Deposited On:||21 Dec 2009 14:35|
|Last Modified:||03 Nov 2015 21:42|
Actions (login required)