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Switching sensitive driver circuit to combat dynamic delay in on-chip buses

Weerasekera, Roshan and Zheng, Li-Rong and Pamunuwa, Dinesh Bandara and Tenhunen, Hannu (2005) Switching sensitive driver circuit to combat dynamic delay in on-chip buses. In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Lecture Notes in Computer Science . Springer, Berlin, pp. 277-285. ISBN 9783540290131

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Abstract

In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it’s drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.

Item Type: Contribution in Book/Report/Proceedings
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Departments: Faculty of Science and Technology > Engineering
ID Code: 31135
Deposited By: Mr Michael Dunne
Deposited On: 21 Dec 2009 14:35
Refereed?: No
Published?: Published
Last Modified: 22 Oct 2014 10:25
Identification Number:
URI: http://eprints.lancs.ac.uk/id/eprint/31135

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