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Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits.

Weldezion, A. and Weerasekera, Roshan and Pamunuwa, Danesh B. and Zheng, Li-Rong and Tenhunen, Hannu (2009) Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits. In: Workshop Notes, Design, Automation and Test in Europe (DATE). UNSPECIFIED, Nice.

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    Item Type: Contribution in Book/Report/Proceedings
    Subjects: T Technology > TA Engineering (General). Civil engineering (General)
    Departments: Faculty of Science and Technology > Engineering
    ID Code: 31108
    Deposited By: Mr Michael Dunne
    Deposited On: 18 Dec 2009 16:15
    Refereed?: No
    Published?: Published
    Last Modified: 26 Jul 2012 21:42
    Identification Number:
    URI: http://eprints.lancs.ac.uk/id/eprint/31108

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