Pamunuwa, Dinesh B. and Öberg, Johnny and Millberg, Mikael and Zheng, Li-Rong and Jantsch, Axel and Tenhunen, Hannu (2004) A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integration: The VLSI Journal, 38 (1). pp. 3-17. ISSN 0167-9260Full text not available from this repository.
On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.
|Journal or Publication Title:||Integration: The VLSI Journal|
|Additional Information:||One of the most promising architectures for trillion device electronic systems is the Network-On-Chip architecture. Although many other papers described high-level protocols and architectural issues, this paper was the first in the literature to address the performance of the on-chip network, under the physical constraints of interconnections in the deep sub micrometer regime. This paper derives critical cost and performance metrics and shows the role of the network bandwidth in dictating system perfomance. RAE_import_type : Journal article RAE_uoa_type : General Engineering|
|Subjects:||T Technology > TA Engineering (General). Civil engineering (General)|
|Departments:||Faculty of Science and Technology > Engineering|
|Deposited On:||27 Mar 2008 09:33|
|Last Modified:||26 Jul 2012 16:35|
Actions (login required)