Bratt, Adrian and Harvey, R. J. A. and Dorey, A. P. and Richardson, A. M. D. (1993) Design-for-test structure to facilitate test vector application with low performance loss in non-test mode. IEE Electronics Letters, 29 (16). pp. 1438-1440.
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Official URL: http://dx.doi.org/10.1049/el:19930963
Abstract
A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1].
| Item Type: | Article |
|---|---|
| Journal or Publication Title: | IEE Electronics Letters |
| Additional Information: | "©1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." |
| Subjects: | T Technology > TA Engineering (General). Civil engineering (General) |
| Departments: | Faculty of Science and Technology > Engineering |
| ID Code: | 20609 |
| Deposited By: | ep_ss_importer |
| Deposited On: | 02 Dec 2008 11:11 |
| Refereed?: | No |
| Published?: | Published |
| Last Modified: | 26 Jul 2012 15:39 |
| Identification Number: | |
| URI: | http://eprints.lancs.ac.uk/id/eprint/20609 |
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