Bratt, Adrian and Olbrich, T. and Dorey, A. P. (1994) Class AB cascode current memory cell. IEE Electronics Letters, 30 (22). pp. 1821-1823.
The presented sampled-current memory cell demonstrates class AB operation where the bipolar input current magnitude may exceed twice the quiescent bias current even though full cascode regulation is maintained. Calculation of the necessary safety margin to accommodate process tolerances is shown to be simplified compared with the standard regulated cascode cell.
|Item Type: ||Article|
|Journal or Publication Title: ||IEE Electronics Letters|
|Additional Information: ||"©1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."|
|Uncontrolled Keywords: ||bipolar integrated circuits ; cascade networks ; integrated memory circuits ; switched networks|
|Subjects: ||T Technology > TA Engineering (General). Civil engineering (General)|
|Departments: ||Faculty of Science and Technology > Engineering|
|ID Code: ||20516|
|Deposited By: ||ep_ss_importer|
|Deposited On: ||05 Dec 2008 14:45|
|Last Modified: ||26 Jul 2012 15:39|
|Identification Number: |
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