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Clock switching:a new design for current test (DcT) method for dynamic logic circuits

Rosing, R. and Richardson, A. M. D. and Kerkhoff, A. and Acosta, A. (1998) Clock switching:a new design for current test (DcT) method for dynamic logic circuits. In: IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on. IEEE, pp. 20-25. ISBN 0818691913

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Abstract

Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults

Item Type: Contribution in Book/Report/Proceedings
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Departments: Faculty of Science and Technology > Engineering
ID Code: 20389
Deposited By: ep_ss_importer
Deposited On: 17 Dec 2008 14:37
Refereed?: No
Published?: Published
Last Modified: 09 Apr 2015 09:50
Identification Number:
URI: http://eprints.lancs.ac.uk/id/eprint/20389

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